As CMOS technology continues to scale further into the submicron region, the width of the gate on metal oxide semiconductor (MOS) transistors and the thickness of the gate oxide are constantly being reduced. MOS transistor gates are formed using a conductive material such as metals, silicides, and doped polycrystalline silicon (polysilicon). For MOS transistor gates formed using doped polysilicon, metal silicides are often formed on the gate structure to reduce the sheet resistance of the gate and to ensure proper electrical contract.
The self-aligned processes used to fabricate MOS transistors and other processes require the formation of a sidewall structure. Along with the reduction in MOS transistor gate width, the scaling of CMOS technology also requires that the width of the sidewall structures be reduced. Gate fabrication techniques utilize an etching process, such as plasma etching or wet chemical etching, to chemically remove material to form the microelectronic devices.
Some etching processes used in fabricating the gate remove material that would otherwise be beneficial to the construction or operation of the microelectronic device. For example, as illustrated in FIG. 3A, a polysilicon gate 402 including a thin gate oxide layer 403 is formed on a substrate 404. To form the sidewalls, an oxide layer 406 and a nitride layer 408 are formed over gate 402 and substrate 404. As illustrated in FIG. 3B, to form the gate sidewalls, nitride layer 408 is typically etched by using a plasma etch process which does not completely stop on oxide layer 406, but etches away oxide layer 406 and a portion of substrate 404, creating a recess 410 in substrate 404. Additionally, as illustrated in FIG. 3B, a subsequent oxidation step, which is used to remove the plasma etch damage, increases recess 410 because part of the silicon in substrate 404 gets converted to silicon oxide 410. The oxidation step is also referred to as the poly-oxidation or “smile” oxidation step because it creates a “smile” oxide 412 at the edge of the gate. The oxidation step is followed by the offset spacer loop.
The recess in the substrate can degrade the performance of the transistor and increase its variability. A thick smile oxide can reduce overlap capacitance and reduce transistor drive current. It is therefore desirable to minimize the silicon recess and “smile oxide” in the fabrication of the transistor structure. The present teachings provide several fabrication techniques to minimize the recess and smile oxide and improve performance.